> ## Documentation Index
> Fetch the complete documentation index at: https://olympus.etched.com/llms.txt
> Use this file to discover all available pages before exploring further.

# IP Partners

An overview of the pre-built intellectual property (IP) blocks we acquire from third parties and our relationship with said parties.

<Tip>
  * IP is often bundled in w/ backend services for our larger partners (e.g. Alphawave for Sohu, Broadcom for Chronos)
  * Some IP arrives directly under our own contract (e.g. Arm CPU cores, Synopsys DesignWare), and some arrives via another partner under a multi-party NDA (e.g. Rambus controllers come through Broadcom)
</Tip>

<Tabs>
  <Tab title="Broadcom">
    <Card title="Broadcom Vendor Card" icon="cards-blank">
      Largest IP supplier on the IO die. High-speed, mixed-signal, foundation IP, including:

      * Standard cell library
      * SRAM memory compilers
      * SerDes + Ethernet controller
      * PCIe link (Gen 6)
      * PLLs (clock generators) and GPIOs (input/output pins)

      <Accordion title="Other Products">
        - Very extensive catalog, including newer SerDes generations, more protocol controllers, optics IP for future gen
        - Cross-selling to platform team: NICs, switches, and optical technologies
      </Accordion>

      <Accordion title="Past Experience">
        * Chronos is our first-time using Broadcom IP! Prev-gen Sohu chip used Alphawave PHYs and IP more heavily
        * Broadcom is known for being the gold standard in the industry
      </Accordion>

      <Accordion title="Contact Info">
        * Harold Gomard: Main PoC for (business only, not technical)

        \--

        * John Wang: Eng Ops lead + Etched-side POC
        * Ankur Shah / Omid Azarnik / Jaidon Hill: RTL owners for Ethernet
        * Ankur Shah / Rajesh Rao / [<u>Chandu Yuvarajappa</u>](mailto:chandu@etched.com): RTL owners for PCIe
        * Ankur Shah / Carson Robles / Yan Zhang: RTL owners for PLLs / clocking
        * Artem Vasilyev / Carson Robles: RTL owners for cSRAM
        * Saptadeep Pal: Ultimate executive sponsor
      </Accordion>

      <Accordion title="Notes">
        * Harold/Eli own both the IP and design services relationship and sales conversations often bundle the two
        * See previous notes on 3/4-way NDA
      </Accordion>
    </Card>
  </Tab>

  <Tab title="Arm">
    <Card title="Arm Vendor Card" icon="cards-blank">
      * Supplier for Chronos compute-die CPU subsystem (CPU\_SS)
      * Dual-core Neoverse E1 with some supporting interconnects and IPs
      * Supporting tooling: Socrates for IP config, Arm Development Studio for compilers

      <Accordion title="Other Products">
        - Newer Neoverse cores for future products
      </Accordion>

      <Accordion title="Past Experience">
        * First time working with Arm, good experience so far
      </Accordion>

      <Accordion title="Contact Info">
        * n/a

        \--

        * John Wang: Eng Ops lead + Etched-side POC
        * Nikhil Gopalakrishna / Yi Sun: RTL leads for CPU\_SS
        * Ankur Shah: Head of SoC RTL, has prior Arm IP config experience
        * Murtaza Saifuddin, Santosh Pokala: CPU\_SS verification + integration
      </Accordion>
    </Card>
  </Tab>

  <Tab title="Rambus">
    <Card title="Rambus Vendor Card" icon="cards-blank">
      Supplier of key memory controllers on compute and IO dies, including:

      * HBM4 controller, paired with Broadcom HBM4 PHY
      * PCIe Gen6 controller, paired with Broadcom PCIe (Gen 6) SerDes

      <Accordion title="Other Products">
        - Memory IP beyond HBM4 standard (e.g. DDR5 and HBM5)
      </Accordion>

      <Accordion title="Past Experience">
        * No prior history before Chronos
        * IP arrives via Broadcom contracts, often with limited internal visibility
      </Accordion>

      <Accordion title="Contact Info">
        * Bunninder Falak ([<u>bfalak@rambus.com</u>](mailto:bfalak@rambus.com)): Main PoC
        * Miguel Costa ([mcosta@rambus.com](mailto:mcosta@rambus.com)): Application Engineer
        * Mark Wagner ([mwagner@rambus.com](mailto:mwagner@rambus.com)): Application Engineer
        * William Tseng ([<u>witseng@rambus.com</u>](mailto:witseng@rambus.com)); AE Rambus controller

        \--

        * John Wang: Eng Ops lead + Etched-side POC
        * Ankur Shah: Memory controller owner
        * Santosh Pokhala: DV for memory controller owner
      </Accordion>
    </Card>
  </Tab>

  <Tab title="SK Hynix">
    <Card title="SK Hynix Vendor Card" icon="cards-blank">
      They are our memory supplier and provide us with:

      * The HBM stacks that sit on our package and make up East/West HBM
      * Sohu used HBM3E, Chronos uses HBM4 (6 x 12H 36GB stacks at 12G/s per pin)

      <Accordion title="Other Products">
        - Future HBM generations and higher-quality HBM grades as we scale
      </Accordion>

      <Accordion title="Past Experience">
        * Strong working relationship across 2 gens of chips
      </Accordion>

      <Accordion title="Contact Info">
        * Eunseo Kim ([<u>eunseo1.kim@sk.com</u>](mailto:eunseo1.kim@sk.com)): Main POC

        \--

        * John Wang: Eng Ops lead + Etched-side POC
        * Brian Loiler: VP platform, HBM debug program
        * Chensheng Wang: Memory engagement and roadmap conversations
      </Accordion>
    </Card>
  </Tab>

  <Tab title="Synopsys / Ansys">
    <Card title="Synopsys / Ansys Vendor Card" icon="cards-blank">
      * Provides DesignWare (DW) IP (basic gates, sync cells, FIFOs, clock gates, etc.)
      * Includes DW AXI and interface IP

      <Accordion title="Other Products">
        - Broader DesignWare catalog
        - PCIe/USB controllers + memory controllers
      </Accordion>

      <Accordion title="Past Experience">
        * Genus synthesis has known compatibility issues with DW foundational IP

        <Warning>
          The idea behind DW IP is to provide us designs that have very basic functionality (e.g. matrix multiply) but have proven ability to integrate nicely in silicon.

          However, **using outside IP is not efficient PPA-wise** and, long-term, design of these IPs can/will move in house
        </Warning>
      </Accordion>

      <Accordion title="Contact Info">
        * George Adzich: Commercial / NDA PoC
        * Karan Shah: Application Engineer

        \--

        * John Wang: Eng Ops lead + Etched-side POC
        * Siva Mandadi: Installation, license management, IP regen
        * Nikhil Gopalakrishna: RTL user of DW IP for CPU\_SS
        * Anru Wang, Artem Vasilyev: Internal IP leaders whose teams use DW IP
      </Accordion>

      <Accordion title="Notes">
        * N/A
      </Accordion>
    </Card>
  </Tab>
</Tabs>