IP Partners - Etched

Broadcom Vendor Card

Largest IP supplier on the IO die. High-speed, mixed-signal, foundation IP, including:

Standard cell library
SRAM memory compilers
SerDes + Ethernet controller
PCIe link (Gen 6)
PLLs (clock generators) and GPIOs (input/output pins)

Other Products

Very extensive catalog, including newer SerDes generations, more protocol controllers, optics IP for future gen
Cross-selling to platform team: NICs, switches, and optical technologies

Past Experience

Chronos is our first-time using Broadcom IP! Prev-gen Sohu chip used Alphawave PHYs and IP more heavily
Broadcom is known for being the gold standard in the industry

Contact Info

Harold Gomard: Main PoC for (business only, not technical)

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John Wang: Eng Ops lead + Etched-side POC
Ankur Shah / Omid Azarnik / Jaidon Hill: RTL owners for Ethernet
Ankur Shah / Rajesh Rao / Chandu Yuvarajappa: RTL owners for PCIe
Ankur Shah / Carson Robles / Yan Zhang: RTL owners for PLLs / clocking
Artem Vasilyev / Carson Robles: RTL owners for cSRAM
Saptadeep Pal: Ultimate executive sponsor

Notes

Harold/Eli own both the IP and design services relationship and sales conversations often bundle the two
See previous notes on 3/4-way NDA

Arm Vendor Card

Supplier for Chronos compute-die CPU subsystem (CPU_SS)
Dual-core Neoverse E1 with some supporting interconnects and IPs
Supporting tooling: Socrates for IP config, Arm Development Studio for compilers

Other Products

Newer Neoverse cores for future products

Past Experience

First time working with Arm, good experience so far

Contact Info

n/a

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John Wang: Eng Ops lead + Etched-side POC
Nikhil Gopalakrishna / Yi Sun: RTL leads for CPU_SS
Ankur Shah: Head of SoC RTL, has prior Arm IP config experience
Murtaza Saifuddin, Santosh Pokala: CPU_SS verification + integration

Rambus Vendor Card

Supplier of key memory controllers on compute and IO dies, including:

HBM4 controller, paired with Broadcom HBM4 PHY
PCIe Gen6 controller, paired with Broadcom PCIe (Gen 6) SerDes

Other Products

Memory IP beyond HBM4 standard (e.g. DDR5 and HBM5)

Past Experience

No prior history before Chronos
IP arrives via Broadcom contracts, often with limited internal visibility

Contact Info

Bunninder Falak (bfalak@rambus.com): Main PoC
Miguel Costa (mcosta@rambus.com): Application Engineer
Mark Wagner (mwagner@rambus.com): Application Engineer
William Tseng (witseng@rambus.com); AE Rambus controller

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John Wang: Eng Ops lead + Etched-side POC
Ankur Shah: Memory controller owner
Santosh Pokhala: DV for memory controller owner

SK Hynix Vendor Card

They are our memory supplier and provide us with:

The HBM stacks that sit on our package and make up East/West HBM
Sohu used HBM3E, Chronos uses HBM4 (6 x 12H 36GB stacks at 12G/s per pin)

Other Products

Future HBM generations and higher-quality HBM grades as we scale

Past Experience

Strong working relationship across 2 gens of chips

Contact Info

Eunseo Kim (eunseo1.kim@sk.com): Main POC

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John Wang: Eng Ops lead + Etched-side POC
Brian Loiler: VP platform, HBM debug program
Chensheng Wang: Memory engagement and roadmap conversations

Synopsys / Ansys Vendor Card

Provides DesignWare (DW) IP (basic gates, sync cells, FIFOs, clock gates, etc.)
Includes DW AXI and interface IP

Other Products

Broader DesignWare catalog
PCIe/USB controllers + memory controllers

Past Experience

Genus synthesis has known compatibility issues with DW foundational IP

The idea behind DW IP is to provide us designs that have very basic functionality (e.g. matrix multiply) but have proven ability to integrate nicely in silicon.However, using outside IP is not efficient PPA-wise and, long-term, design of these IPs can/will move in house

Contact Info

George Adzich: Commercial / NDA PoC
Karan Shah: Application Engineer

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John Wang: Eng Ops lead + Etched-side POC
Siva Mandadi: Installation, license management, IP regen
Nikhil Gopalakrishna: RTL user of DW IP for CPU_SS
Anru Wang, Artem Vasilyev: Internal IP leaders whose teams use DW IP

Notes

N/A