> ## Documentation Index
> Fetch the complete documentation index at: https://olympus.etched.com/llms.txt
> Use this file to discover all available pages before exploring further.

# EDA Tools

An overview of the Electronic Design Automation (EDA) tools we use throughout the chip design process + the "Big 3" players we work with.

<Tip>
  The below is a high-level overview. For a more exhaustive list of EDA tools, alternatives, and notes, [refer to this sheet](https://docs.google.com/spreadsheets/d/1pjV2iFt0MfWWuPnXQj67Fbl7sIhOc47IzZnzRpvmyrU/edit?gid=0#gid=0)
</Tip>

<Tabs>
  <Tab title="Cadence EDA">
    <Card title="Cadence EDA Vendor Card" icon="cards-blank">
      Largest vendor we purchase from. Their tools are used in almost every stage of the process but particularly on the backend.

      Key tools in use include:

      * Genus (for synthesis of RTL → netlist)
      * Innovus (for physical placement of cells + routing of wiring)
      * Joules/Voltus (for power analysis

      <Accordion title="Contact Info">
        - Sruba Seshadri ([<u>sruba@cadence.com</u>](mailto:sruba@cadence.com)): EDA tools account contact
        - Rajyug ([<u>rajyug@cadence.com</u>](mailto:rajyug@cadence.com)): EDA tools account contact
        - Govind P ([<u>govindp@cadence.com</u>](mailto:govindp@cadence.com)), Wei-Chun Chou ([<u>wchou@cadence.com</u>](mailto:wchou@cadence.com)): Application Engineers, also active for Cadence Design Services engagement

        \--

        * Ram Itani: Etched-side POC
      </Accordion>
    </Card>

    <Info>
      **Notes**

      We are evaluating many other Cadence tools as alternatives to Synopsys tools, due to better pricing for short-term demand spikes.

      Ram Itani is monitoring this and has context.
    </Info>
  </Tab>

  <Tab title="Synopsys/Ansys">
    <Card title="Synopsys Vendor Card" icon="cards-blank">
      Second largest EDA relationship with tools scattered throughout the chip dev stack.

      Key tools in use include:

      * VCS + Verdi (for RTL sim, i.e. verifying functional correctness)
      * SpyGlass (for clock domain crossing and reset clock crossing checks)
      * TestMAX (DFT, confirming RTL is testable)
      * ZeBu (for emulation)

      <Accordion title="Contact Info">
        - George Adzich ([<u>george.adzich@synopsys.com</u>](mailto:george.adzich@synopsys.com)): Primary contract and NDA owner
        - Karan Shah ([<u>karan.shah@synopsys.com</u>](mailto:karan.shah@synopsys.com)): Application engineering contact

        \--

        * John Wang: EngOps lead + Etched-side PoC
      </Accordion>
    </Card>

    <Card title="Ansys Vendor Card" icon="cards-blank">
      Mainly used for physics and mechanical / thermal simulation software. Less applicable to ASIC, more used by platform and other teams.

      Main ASIC tool in use:

      * RedHawk SC (for power signoff and IR drop sim)

      <Accordion title="Contact Info">
        - Bob Calvin ([Bob.Calvin@synopsys.com](mailto:Bob.Calvin@synopsys.com)): Main PoC

        \--

        * Ram Itani: Etched-side PoC
      </Accordion>
    </Card>

    <Info>
      **Notes**

      Ansys was acquired by Synopsys in 2024/2025. Currently we treat them as separate accounts but expect bundling conversations at renewal time.
    </Info>
  </Tab>

  <Tab title="Siemens">
    <Card title="Siemens Vendor Card" icon="cards-blank">
      Smallest of our "Big 3" EDA tool providers but extensively used in DFT flow.

      Key tools in use include:

      * Calibre (DRC rule checking to ensure chip meets design and manufacturability constraints)
      * Tessent (for inserting key test infrastructure into chip design)

      <Accordion title="Contact Info">
        - Amgad Fouad ([<u>amgad.fouad@siemens.com</u>](mailto:amgad.fouad@siemens.com)): Primary PoC + contract/NDA owner
      </Accordion>
    </Card>

    <Info>
      **Notes**

      * Tessent licenses come in many narrow feature flavours. When purchasing, be careful to cover the specific `tessent-*` features your flow needs
      * For Chronos, major parts of the DFT process are contracted out to Broadcom. The DFT team is concerned about over-reliance on Broadcom and is developing the internal Tessent-based flow in parallel
    </Info>
  </Tab>

  <Tab title="Others">
    <Card title="Misc EDA Tools Card" icon="cards-blank">
      There are many notable one-off vendors in our stack, including:

      <Card title="RealIntent" type="info">
        * AscentLint (our primary lint tool for flagging basic violations, errors, and bugs before compile time)
        * POC: Manas ([<u>manas@realintent.com</u>](mailto:manas@realintent.com))

        <Warning>
          #### Lint license expiry should be treated as a P0/P1 issue, since it blocks the CI pipeline.
        </Warning>
      </Card>

      <Card title="AMIQ" type="info">
        * HDL IDE (lint front-end that links our linting tools to VS Code / Eclipse so that engineers can run easily)
        * POC: Cristian Amitroaie ([<u>cristian@amiq.com</u>](mailto:cristian@amiq.com))
      </Card>

      <Card title="Baum" type="info">
        * For clock-gating efficiency profiling, to spot RTL-level power wastage
        * POC: Seungwhun Paik ([<u>seungwhun.paik@baum-ds.com</u>](mailto:seungwhun.paik@baum-ds.com))

        <Note>
          CG analysis is opt-in per block. Managers (Ankur, Artem) own opt-in/opt-out and will update the CG report when their module is reviewed
        </Note>
      </Card>
    </Card>
  </Tab>

  <Tab title="Links">
    * [Comprehensive EDA tools overview](https://docs.google.com/spreadsheets/d/1pjV2iFt0MfWWuPnXQj67Fbl7sIhOc47IzZnzRpvmyrU/edit?gid=0#gid=0)
    * [License renewals folder](https://drive.google.com/drive/folders/1nES4keVpgcD46mdtOAIGXsnm8hfMy_CU?usp=sharing)
    * [EDA rate cards](https://drive.google.com/drive/folders/18RVPT4a7dEF_z4ZHF2LEdek5VTW5JGVI?usp=sharing)
    * [License demand estimates](https://docs.google.com/spreadsheets/d/1XCMmwKuTi-1XetQWkxPWxaITuKBjF9a_96l46pyoYXQ/edit?gid=405456716#gid=405456716\&fvid=113792866)
    * [Rate card negotiation model](https://docs.google.com/spreadsheets/d/100tEkG9k9nf3iAYVFbrdid9e69zS9gnbCUUXht98mHM/edit?gid=1488358244#gid=1488358244) (Synopsys is the example here)

    Message John Wang, Shasi Pinninti, Grace Qi, or Ram Itani for any questions about EDA tool licenses / renewals!
  </Tab>
</Tabs>