EDA Tools - Etched

Cadence EDA Vendor Card

Largest vendor we purchase from. Their tools are used in almost every stage of the process but particularly on the backend.Key tools in use include:

Genus (for synthesis of RTL → netlist)
Innovus (for physical placement of cells + routing of wiring)
Joules/Voltus (for power analysis

Contact Info

Sruba Seshadri (sruba@cadence.com): EDA tools account contact
Rajyug (rajyug@cadence.com): EDA tools account contact
Govind P (govindp@cadence.com), Wei-Chun Chou (wchou@cadence.com): Application Engineers, also active for Cadence Design Services engagement

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Ram Itani: Etched-side POC

NotesWe are evaluating many other Cadence tools as alternatives to Synopsys tools, due to better pricing for short-term demand spikes.Ram Itani is monitoring this and has context.

Synopsys Vendor Card

Second largest EDA relationship with tools scattered throughout the chip dev stack.Key tools in use include:

VCS + Verdi (for RTL sim, i.e. verifying functional correctness)
SpyGlass (for clock domain crossing and reset clock crossing checks)
TestMAX (DFT, confirming RTL is testable)
ZeBu (for emulation)

Contact Info

George Adzich (george.adzich@synopsys.com): Primary contract and NDA owner
Karan Shah (karan.shah@synopsys.com): Application engineering contact

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John Wang: EngOps lead + Etched-side PoC

Ansys Vendor Card

Mainly used for physics and mechanical / thermal simulation software. Less applicable to ASIC, more used by platform and other teams.Main ASIC tool in use:

RedHawk SC (for power signoff and IR drop sim)

Contact Info

Bob Calvin (Bob.Calvin@synopsys.com): Main PoC

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Ram Itani: Etched-side PoC

NotesAnsys was acquired by Synopsys in 2024/2025. Currently we treat them as separate accounts but expect bundling conversations at renewal time.

Siemens Vendor Card

Smallest of our “Big 3” EDA tool providers but extensively used in DFT flow.Key tools in use include:

Calibre (DRC rule checking to ensure chip meets design and manufacturability constraints)
Tessent (for inserting key test infrastructure into chip design)

Contact Info

Amgad Fouad (amgad.fouad@siemens.com): Primary PoC + contract/NDA owner

Notes

Tessent licenses come in many narrow feature flavours. When purchasing, be careful to cover the specific tessent-* features your flow needs
For Chronos, major parts of the DFT process are contracted out to Broadcom. The DFT team is concerned about over-reliance on Broadcom and is developing the internal Tessent-based flow in parallel

Misc EDA Tools Card

There are many notable one-off vendors in our stack, including:

RealIntent

AscentLint (our primary lint tool for flagging basic violations, errors, and bugs before compile time)
POC: Manas (manas@realintent.com)

Lint license expiry should be treated as a P0/P1 issue, since it blocks the CI pipeline.

AMIQ

HDL IDE (lint front-end that links our linting tools to VS Code / Eclipse so that engineers can run easily)
POC: Cristian Amitroaie (cristian@amiq.com)

Baum

For clock-gating efficiency profiling, to spot RTL-level power wastage
POC: Seungwhun Paik (seungwhun.paik@baum-ds.com)

CG analysis is opt-in per block. Managers (Ankur, Artem) own opt-in/opt-out and will update the CG report when their module is reviewed

Comprehensive EDA tools overview
License renewals folder
EDA rate cards
License demand estimates
Rate card negotiation model (Synopsys is the example here)

Message John Wang, Shasi Pinninti, Grace Qi, or Ram Itani for any questions about EDA tool licenses / renewals!

Cadence EDA Vendor Card

Synopsys Vendor Card

Ansys Vendor Card

Siemens Vendor Card

Misc EDA Tools Card

RealIntent

​Lint license expiry should be treated as a P0/P1 issue, since it blocks the CI pipeline.

AMIQ

Baum

Lint license expiry should be treated as a P0/P1 issue, since it blocks the CI pipeline.