> ## Documentation Index
> Fetch the complete documentation index at: https://olympus.etched.com/llms.txt
> Use this file to discover all available pages before exploring further.

# Contractors & Backend Partners

<Info>
  **Contractor =**

  * A third party who work under Etched’s day-to-day direction and report to Etched managers
  * Engagement structure: Master MSA between Etched and vendor + per-project SOWs that name contracted engineers + rates (contractors usually have a specific scope and are paid on some time basis)
  * Finite contract length unlike full-time employees
  * Contracts negotiated and owned by ASIC ops, with legal sign-off happening through legal team / legal counsel

  <Warning>
    Rates and legal terms are often different abroad (e.g. India) VS. in the US. Rates abroad are often cheaper than those quoted for the US.

    This is something to keep in mind when negotiating, as many contractors have separate legal entities under the same name in multiple locations globally.
  </Warning>
</Info>

<Tabs>
  <Tab title="VTool">
    <Card title="VTool Contractor Card" icon="cards-blank">
      * Currently our largest DV contractor
      * Working on IO die DV (Ethernet, Datalink, D2D NoC, PCIe, FSU, PLL, NLU)
      * Headquartered in Tel Aviv with engineers distributed across Eastern Europe

      <Accordion title="Past experiences">
        - Mixed: Engineers are productive but communication / iteration is challenging due to time zone differences
      </Accordion>

      <Accordion title="Contacts + Etched POC">
        * Hagai Arbel ([<u>hagai@thevtool.com</u>](mailto:hagai@thevtool.com)): Main PoC

        \--

        * Grace Qi: Etched-side POC
      </Accordion>

      <Accordion title="Materials">
        * [VTool folder](https://drive.google.com/drive/folders/1O6MaTVBSqYiKspjbFkZa2HEFoIDk-y3R?usp=drive_link)
        * [VTool mutual NDA](https://drive.google.com/file/d/1arxXBrOZ_VUTez2_XWqDkKQe_F0bDs_q/view?usp=drive_link)
        * [VTool MSA](https://drive.google.com/file/d/1IFawaWte7mg5pFKGxLbU9mr6BZSDMRN4/view?usp=drive_link)
      </Accordion>

      <Accordion title="Notes">
        n/a
      </Accordion>
    </Card>
  </Tab>

  <Tab title="Lubis">
    <Card title="Lubis Contractor Card" icon="cards-blank">
      * Design verification contractor, specifically formal verification specialists
      * Working on IO die blocks (NoC router, SerDes, FIFOs

      <Accordion title="Past experiences">
        - Good experience so far, considering ramping from 1 to 3 engineers
      </Accordion>

      <Accordion title="Contacts + Etched POC">
        * Max Birtel ([<u>Max.Birtel@lubis-eda.com</u>](mailto:Max.Birtel@lubis-eda.com)): Main PoC

        \--

        * Grace Qi: Etched-side POC
      </Accordion>

      <Accordion title="Materials">
        * [Lubis folder](https://drive.google.com/drive/folders/12_XTSBByXc4_c2Jid2s4IeS1R0FEPG9O)
        * Refer to #lubis-noc and #lubis-common Slack channels
      </Accordion>

      <Accordion title="Notes">
        * Lubis contractors consume VC Formal licenses from Synopsys: something to keep in mind if we scale up
        * Can drop below 3 FTEs for up to 3 months with no penalty
        * Decrease in headcount requires 90 days’ notice
      </Accordion>
    </Card>
  </Tab>

  <Tab title="Eximietas">
    <Card title="Eximietas Contractor Card" icon="cards-blank">
      * Long-running contractor relationship, engaged since Sohu era
      * Sohu scope: firmware verification of CUP\_SS and peripherals
      * Chronos scope: DFT flow execution alongside internal DFT team

      <Accordion title="Past experiences">
        - Good, team has good built-up knowledge of codebase and DFT flow
      </Accordion>

      <Accordion title="Contacts + Etched POC">
        * Ameya Mitragotri: Main POC
        * Anwar Hussain: Sales Head, APAC + commercial contact
        * Arun George: Head, Embedded Software

        \--

        * John Wang: Eng Ops lead + Etched-side POC
      </Accordion>

      <Accordion title="Materials">
        * [Eximietas folder](https://drive.google.com/drive/folders/18e1VjbSSLJbjhzF_h2-gaENzeJAZOxVB)
        * Refer to #chronos-dft-etched-eximietas
      </Accordion>

      <Accordion title="Notes">
        * Eximietas contractors use Synopsys DVE for waveform debug rather than Cadence Verdi (which we use internally)
        * Better rate than vTool or Lubis since services are delivered from India
        * Net 30 payment standard instead of Net 60. Potentially worth re negotiating for any new SOWs
      </Accordion>
    </Card>
  </Tab>

  <Tab title="EIC">
    <Card title="eInfoChips Contractor Card" icon="cards-blank">
      * New contractor. Only 1 contractor at the moment, working on PCIe DV
      * Could be a likely candidate for future PD and DV support

      <Warning>
        They are our only contractor with capped liability for breach of confidentiality. This is a serious financial/legal risk for us if they leak IP from our 3rd party vendors, as we take sole responsibility on those contracts.

        Thus, take extra caution in onboarding contractors from EIC.
      </Warning>

      <Accordion title="Past experiences">
        * N/A
      </Accordion>

      <Accordion title="Contacts + Etched POC">
        * Vipin Choudhry ([Vipin.Choudhry@einfochips.com](mailto:Vipin.Choudhry@einfochips.com)): Main POC

        \--

        * Grace Qi: Eng Ops + Etched-side POC
      </Accordion>
    </Card>
  </Tab>

  <Tab title="LTTS">
    <Card title="LTTS Contractor Card" icon="cards-blank">
      <Warning>
        **Currently in negotiation process - ask John and Ram for latest updates**

        Major negotiation(s) sticking point is an upper cap on liabilities in the event contractors leak IP. Same issue as EIC

        Most likely will result in a compromise and less favorable security terms for Etched: a risk to keep in mind
      </Warning>
    </Card>
  </Tab>

  <Tab title="7 Rays">
    <Card title="7Rays Semiconductor Contractor Card" icon="cards-blank">
      * Long-standing staffing vendor. Chronos scope: Staffing in-person PD contractors
      * Broad ASIC staffing services across design, DV, PD, DFT, and verification

      <Accordion title="Past experiences">
        - Ok. One of the main reasons we’ve used them is a big gap in ASIC recruiter headcount internally
        - Would prefer not to rely on them long term
      </Accordion>

      <Accordion title="Contacts + Etched POC">
        * Sai Harsha Nalgonda ([<u>harsha@7rayssemi.com</u>](mailto:harsha@7rayssemi.com)): Technical PoC
        * [<u>Vijay Mohan</u>](mailto:vijay@7rayssemi.com) ([<u>vijay@7rayssemi.com</u>](mailto:vijay@7rayssemi.com)): Legal PoC

        \--

        * John Wang: Eng Ops lead + Etched-side POCs
        * Ram Itani: Etched-side POC
      </Accordion>

      <Accordion title="Notes">
        * Since MSA/MNDA is already signed, re-engaging them can be spun up quickly (only requires drafting a new SoW)
      </Accordion>
    </Card>
  </Tab>

  <Tab title="ACL Digital">
    <Card title="ACL Digital Contractor Card" icon="cards-blank">
      * Our second staffing vendor. Helps with PD and DV resourcing
      * Newer engagement than 7Rays 
      * Helps with DV and PD resourcing. Currently, we have PD contractors in person and in India from them

      <Accordion title="Contacts + Etched POC">
        - Kumar Boddu ([snspkumar.boddu@acldigital.com](mailto:snspkumar.boddu@acldigital.com)): Technical PoC
        - Sandeep Gandhi ([<u>sandeep.gandhi@acldigital.com</u>](mailto:sandeep.gandhi@acldigital.com)): Legal PoC

        \--

        * Ram Itani: Etched-side POC
        * John Wang: Eng Ops lead + Etched-side POC
      </Accordion>

      <Accordion title="Notes">
        * As mentioned in the contractor hiring guide, be careful which entity you engage (US or India)
          * US MSA does not automatically cover Indian entity and vice versa
        * Confirm with Ram/John on our MSA coverage before engaging
      </Accordion>
    </Card>
  </Tab>
</Tabs>

<Info>
  **Backend partner =**

  * Whole companies we hire to *do* part of the design of the chip (physical design, DFT insertion, packaging, etc.)
  * Usually a whole team of engineers are assigned to the project. They report to the managers at the backend partner company, not directly to Etched managers
  * Engineers at these companies impact our chip’s actual design. Contrast this with EDA or IP where the company sells us blocks/tooling that our internal engineers use
</Info>

<Tabs>
  <Tab title="Alphawave">
    <Card title="Alphwave Vendor Card" icon="cards-blank">
      * The partner that took Sohu (our first chip) from RTL through tape-out, and supplies the high-speed PHYs we are still using
      * Areas of focus include synthesis, P\&R (place & route), STA (static timing analysis)
      * Ongoing Sohu post-silicon support

      <Accordion title="Past experiences">
        - Mixed bag but mostly ok relationship
        - High need for follow-ups and ineffective direct-to-engineers communication
          * At one point, executive team + ops + selected engineers travelled onsite to Bangalore to own Sohu closeout
      </Accordion>

      <Accordion title="Contacts + Etched POC">
        * Ravi Selvaraj ([<u>ravi.selvaraj@awavesemi.com</u>](mailto:ravi.selvaraj@awavesemi.com)): PoC

        \--

        * Ankur Shah (Head of SoC RTL), Gavin Uberti (CEO), John Wang (Eng Ops Lead), and many others have owned Sohu close-out from Bangalore
      </Accordion>

      <Accordion title="Notes">
        * As mentioned above, primarily a Sohu A0/B0 partner. Not super relevant for Chronos development
        * Company now operates under Qualcomm umbrella, which is why you may see emails from [<u>qti.qualcomm.com</u>](http://qti.qualcomm.com) email addresses. Alphawave Semi naming is still used internally however
      </Accordion>
    </Card>
  </Tab>

  <Tab title="Broadcom">
    <Card title="Broadcom Vendor Card" icon="cards-blank">
      * Backend partner for the Chronos IO die (project codename Alamos)
      * Compute die gate-level DFT (design-for-test) insertion, e.g. Etched sends pre-DFT netlist and Broadcom returns post-DFT
      * Floor planning, Physical Synthesis, Placement, Clock Tree Synthesis, Routing, RC Extraction, Static Timing Analysis, Power, EM, IR, Noise, SI Analysis, Physical Verification (LVS/DRC) for IO die
      * Packaging, substrate, and interposer design (for entire Chronos program)
      * Post-silicon testing: BRCM to own chip screening and binning for Chronos

      <Note>
        Our contract with Broadcom locks us into 2 full packages, with the second starting immediately after the tapeout for Chronos components
      </Note>

      <Accordion title="Past experiences">
        * None! This is our first time using Broadcom for design services
        * They are known to be the gold standard in the industry and, ideally, for future gen chips they would be the preferred partner 
      </Accordion>

      <Accordion title="Contacts + Etched POC">
        * Business/legal/general POC: Harold Gomard ([harold.gomard@broadcom.com](mailto:harold.gomard@broadcom.com))
        * Sales account manager: Eli Avraham ([eli.avraham@broadcom.com](mailto:eli.avraham@broadcom.com))
        * ASIC manager / project manager (Chronos IO die, codename: Alamos): Lakshmi Kandula ([lakshmi.kandula@broadcom.com](mailto:lakshmi.kandula@broadcom.com)) 
        * DFT manager: Bala Ramakrishnan ([bala.ramakrishnan@broadcom.com](mailto:bala.ramakrishnan@broadcom.com))
        * Refer to [<u>kickoff deck</u>](https://drive.google.com/drive/search?q=alamos%20kickoff) for more application engineers + technical contacts

        \--

        * John Wang / Michael Fein: Eng Ops leads + Etched POCs
        * Ram Itani: Eng Ops rep for Alamos and Dakota engagements + Etched POC
        * Zarir Sarkari: Head of PD, owns BRCM delivery
        * Daniel Maung: Head of PD methodologies
        * Suresh Babu M: PD lead for Compute die
        * Sagar Sabade: Head of DFT, runs Broadcom DFT syncs
        * Ankur Shah: Head of SoC RTL
        * Abhijeet Pasumarthy: PoC for file transfer 
        * [<u>Kavya Shivakumar Phirangi</u>](mailto:kavya@etched.com) + [<u>Siva Mandadi</u>](mailto:siva@etched.com): Backups for file transfer
        * Saptadeep Pal: Ultimate executive sponsor
      </Accordion>

      <Accordion title="Materials">
        * [BRCM/CDNS program overview](https://docs.google.com/presentation/d/1r6Phv3rkOrtWgdEuqAosI_m_nhH-VbIYKwkml4o8YAA/edit?slide=id.g3d7717a6681_0_0#slide=id.g3d7717a6681_0_0)
      </Accordion>
    </Card>
  </Tab>

  <Tab title="Cadence Design Services">
    <Card title="Cadence Design Services Vendor Card" icon="cards-blank">
      * Backend partner for the non-compute sections of the Chronos logic die, minus DFT (project codename Dakota)
      * We are delivering RTL drops at three different milestones plus floor plans, library views from Broadcom, gate-level DFT-inserted netlists from Broadcom, etc.
      * Compared to Broadcom, Cadence is not a full design house that owns relationships with fab (TSMC). They will not negotiate allocation, triage supply chain issues, etc.

      <Accordion title="Past experiences">
        - None! This is our first time using for design services
        - Although we have used Cadence EDA tools previously and our Account Manager treats it all as one account
      </Accordion>

      <Accordion title="Contacts + Etched POC">
        * Mahi Arya: Technical Program Manager for Dakota
        * Manoj: India lead
        * Rajesh: Account executive
        * Sunil: IP + services application engineer (AE)
        * Osman Javed: Dakota project sponsor
        * Sandeep Bidadi: Dakota project lead (technical business person, not owning execution)
        * Ashish Shah ([<u>ashah@cadence.com</u>](mailto:ashah@cadence.com)): Lead AE
        * Govind P: AE
        * Wei-Chun Chou: AE

        \--

        * John Wang: Eng Ops lead + Etched side POC
        * Ram Itani: Eng Ops rep for Alamos and Dakota engagements + Etched side POC
        * Daniel Maung: PD methodologies, IO die lead
        * Suresh Babu M: PD lead for compute die
        * Abhijeet Pasumarthy: PoC for file transfer 
        * [<u>Kavya shivakumar Phirangi</u>](mailto:kavya@etched.com) + [<u>Siva Mandadi</u>](mailto:siva@etched.com): Backups for file transfer
      </Accordion>

      <Accordion title="Materials">
        * [BRCM/CDNS program overview](https://docs.google.com/presentation/d/1r6Phv3rkOrtWgdEuqAosI_m_nhH-VbIYKwkml4o8YAA/edit?slide=id.g3d7717a6681_0_0#slide=id.g3d7717a6681_0_0)
      </Accordion>

      <Accordion title="Notes">
        * Cadence Cloud Chamber is a sharked workspace, VPN, PDK, and cloud environment used for some backend execution in this engagement
        * Currently, we have a two-week working session cadence
        * Rajesh cares about holistic Cadence relationship (EDA + services), so rate card, service quality complaints, etc. get bundled
      </Accordion>
    </Card>
  </Tab>
</Tabs>